DARPA Plans to Transform CPU Design, Drive Faster Chips
It’s no secret that general-purpose compute performance has been largely stuck in idle these last few years, with top-end improvements limited to single-digit increases. DARPA has a plan for revitalizing CPU performance by fundamentally changing how we design chips — and it’s an approach that could yield real benefits in at least some areas.
One DARPA concept calls for an overhaul of how we think about CPU architectures. It’s related to a concept we discussed five years ago, in which specific applications could actually be implemented in hardware, potentially offering tremendous performance improvements. It’s also a partial answer to the problem of dark silicon. Moore’s Law has increased transistor density, but without Dennard Scaling we don’t have the ability to turn all of that silicon on at once. One way to use it effectively is to map very specific functions to it that would typically run in the background, but could benefit from running extremely efficiently.
Other architectural concepts being explored include software-defined hardware — hardware that can reconfigure itself at fine-grained timescales to optimally execute workloads based on its analysis of the type of work you’re doing. The other, dubbed “domain specific system on chip,” is an initiative to explore what kinds of common building blocks would need to be present on an SoC to enable effective, flexible, on-the-fly reconfiguration — for, say, radio communication. Are specialized accelerator blocks required, or can the work be done in other ways?
But CPU architectures aren’t the only place where DARPA wants to reinvent computing. As IEEE Spectrum details, its new Craft initiative wants to empower small design teams to build much larger hardware, and to slash the difficulty of moving to a new node by as much as 80 percent. There’s also a set of semiconductor design programs, Idea and Posh, that are attempting to capture the intersection between Electronic Design Automation (EDA) and machine intelligence. Ideally, as you design SoCs, your design software would itself become more intelligent and get better at its job. Posh, meanwhile, is focused on building open source hardware and ensuring a foundation of building blocks is created that can be the basis for any future project.
There’s even more details of how these new initiatives fit into existing IEEE Spectrum projects and how the organization hopes to kickstart research into areas of computing. The article is well worth reading in its entirety. Most of the coverage you see in semiconductors these days often grapples with how engineers are fighting an ever-more difficult battle to wring less and less performance out of silicon. It makes for grim reading on the whole and the day-to-day developments don’t do much to change that.
Initiatives like these emphasize that there are still ideas for how to improve compute performance. They’re still heavily caveated — it’s not at all clear, for example, that anyone will ever build a CPU that actually checks email or performs application functions in hardware. But the effort to build software and hardware that work together more intimately to improve performance is probably a key method we’ll use in the future.
DARPA has previously stated that from 1978 to the present day, CPU architectural improvements account for a 50x improvement in CPU performance, compared with the 1,000x improvement delivered by increased CPU clocks. With CPU clocks stuck below 5GHz and no known near-term improvements expected on that front, finding ways to use the clock speed and configuration options we have more effectively is the only way we’ll keep improving CPU performance.
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