Intel Uses New Foveros 3D Chip-Stacking to Build Core, Atom on Same Silicon
3D chip stacking has long held promise as a meaningful method of advancing silicon performance, but progress in the field has been slow, to say the least. For one thing, CPUs have a nasty tendency to overheat if you stack cores on top of them. Validation has also been a slow, careful process. But at its Tech Day this week, Intel revealed a new technology for connecting components and creating a 3D chip architecture. Codenamed Foveros (a Greek word said to mean fierce or amazing, though I had trouble finding the definition), this new 3D chip-stacking method could revolutionize product designs in the long term. Intel believes it can solve the problems that affect 3D CPU scaling and avoid the thermal issues that can kill these designs.
The chip Intel demoed today was a Foveros-enabled part with a Core CPU and Atom CPU sharing the same physical silicon. If you’re wondering how already in-market capabilities like EMIB compared to Foveros, the answer is that Foveros is a 3D chip stacking solution, while EMIB is designed for 2D stack solutions. The two technologies are not exclusive and we heard word that Intel was planning hardware that would utilize both.
As far as what an actual implementation might look like, the block diagram below shows two separate chips mounted to the same package, via an active interposer layer.
This approach could give Intel tremendous flexibility when it comes to designing parts — a fact the company has already revealed to the public. At the request of a customer, Intel built a CPU with both an Atom and a standard Core processor onboard. This kind of heterogeneous combination has been done before, of course — ARM’s big.Little speaks for itself — but this is the first time we’ve seen it in an Intel CPU. The comparison against big.Little, while obvious, isn’t a particularly good one. Foveros is designed to integrate with a huge range of products and in many different capacities, while big.Little was a specific product implementation intended to reduce power consumption.
The final result of this product is a hybrid x86 architecture that can switch between Core and Atom, both of which are built on 10nm. Logic on the die is contained in the bottom chip, while the CPU cores reside up top. Both AMD and Intel are moving to chiplets, but Intel seems to believe doing them in 3D will allow them to gain additional ground. This unnamed part should launch in 2019 as well.
The combined capabilities of EMIB and Foveros give Intel significant reach and flexibility for wiring up hardware in new and interesting combinations. It’s no accident that we’re seeing AMD reaching for chiplets at the same time. More than three years ago, we wrote an article on Moore’s law, noting that the definition had changed over time as new problems presented themselves. Today, continuing with Moore’s law means continuing to improve scaling, integration, and power consumption. It’s an efficiency game. If Intel can actually start scaling 3D chip production, it could reshape how we design cores in the future.
Continue reading
AMD Has No Near-Term Plan For Hybrid Big, Little Cores on Same Silicon
AMD has no plans to build a hybrid CPU with big and little cores any time in the near future, but the company continues to evaluate the concept.
Silicon Is the New Toilet Paper as Chip Shortage Hits Industrial Manufacturing
The semiconductor shortage is now hitting the industrial computing market, with silicon lead times jumping as high as 50+ weeks depending on the components in question.
Report: Nintendo ‘Switch Pro’ Will Feature DLSS, New Nvidia Silicon
Nintendo's rumored "Switch Pro" will supposedly use Nvidia's DLSS technology to hit 4K resolutions while docked, but it may debut at a higher price point than the original Switch.
Intel’s CEO Travels to Europe to Talk Foundries as Silicon Nationalism Rises
Intel CEO Pat Gelsinger will travel to Europe next week to meet with EU officials about building additional fabs in Europe. This could be part of the EU's effort to take a much larger share of global semiconductor manufacturing by 2030.