EUV Integration at 5nm Still Risky, With Major Problems to Solve

Semiconductor foundries are pushing ahead with extreme ultraviolet lithography (EUV) integration, but there are still formidable barriers to deploying the technology at 5nm and below.

There are several problems that EUV must solve (or continue solving) in order to serve as a replacement for existing 193nm lithography solutions. ASML is still working to develop a pellicle — the membrane that serves as a dust cover over the photomask — that doesn’t absorb too much light. Tools like the NXE 3400B that we saw when we toured GlobalFoundries a few weeks back have support and installation requirements that dwarf conventional lithographic tools, and a corresponding need to deliver dramatically better cost structures to justify their own use.

According to a recent writeup in IEEE Spectrum, the non-profit R&D center Imec, which is a leading research center in EUV lithography, has seen significant problems when using EUV to etch features at 5nm. The rate of stochastic effects is significantly higher than is acceptable for modern manufacturing.

A stochastic effect is an effect that appears randomly, without being linked to a specific dose level, but whose probability is proportional to the strength of the dose. In semiconductors, these effects produce defects that can sabotage or damage a given microprocessor. What Imec has found suggests that these effects are common enough at 5nm to be a major barrier, requiring new approaches to metrology and additional technological solutions. Sometimes, the spaces between the narrow etched trenches were too narrow, leading to so-called ‘microconnections’ between features that aren’t meant to be connected. Other times, necessary features fail to print.

GlobalFoundries showed a diagram suggesting that EUV may be integrated gradually, starting with MOL (middle-of-line), before being integrated into other manufacturing areas. In this model, EUV doesn’t see full integration until 2024 -2026. As EETimes also discusses, there are still barriers to full deployment at virtually every step in the process, from metrology to resists.

The Problem of Perfection

If you want a 10,000-foot overview of the problem, think of it in these terms: Imagine you’ve been asked to draw a straight line with a pencil and a piece of paper. Most people can draw a reasonably straight line free-hand. Now, imagine you’ve been asked to draw an increasingly straight line. First, you reach for a ruler. When that’s no longer sufficient, you might use other mechanical guides.

Eventually, however, that’s no longer enough. You might move to a robotic arm with a perfectly maintained grip and calibrated movement and motion sensors that ensure the line is laid down perfectly. Past that, you might have to find a new type of writing instrument capable of laying down a mark with even less moment-to-moment variation in graphite deposition. You might invest in a specific kind of paper that’s been engineered for less surface variance and superior “flatness.” As the acceptable variance in a straight line moves from “eyeball it” to “nanometers,” the tools you need to generate that line become increasingly complex.

That, in a very large nutshell, is what’s happening in modern lithography. EUV exists because modern feature sizes are so small, they can’t be imaged with existing 193nm lithography without relying on multiple photomasks, which dramatically increases the cost of the device. But EUV is such a fundamentally different approach to what’s been deployed before, it creates an entirely new set of potential problems and interactions with other materials in the manufacturing process, as well as all of the other problems associated with shrinking process nodes and finding more ways to pack transistors more tightly together. As feature sizes shrink, defects that used to have no impact now threaten a design. This has significant implications for chip yields, which in turn has significant implications for chip cost.

Images like the above, which show EUV lithography dramatically reducing costs, are prefaced on the idea that foundries can hit equal yield targets with and without EUV. If EUV yields run lower than conventional lithography yields, that’s going to work directly against any push to move EUV into the mainstream.

EUV is an Economic Play

I want to hit this directly, because I’ve seen this question come up in multiple stories. In many cases, when semiconductor companies announce a manufacturing breakthrough, it’s in the name of making products faster. EUV doesn’t really have any implications for transistor speed, at least not directly.

The reason everyone is charging ahead with EUV is because the economics of semiconductor manufacturing are on a collision course with the fundamental limits of 193nm lithography. Modern chips rely on multiple photomasks to etch their features, in a process referred to as multi-patterning. Today, quadruple pattern is commonly used for 14/16nm devices. But the only way to keep moving downward would be to keep introducing more mask steps. Each mask costs money and each exposure takes time. Chips that used to have 30-40 mask steps might have 70-90 today and well over a hundred in the future. The reason foundries continue to earn substantial amounts of revenue on older process nodes is because many customers see no benefit (and sharply increased costs) from moving to newer nodes. Multi-patterning is a big part of why.

Deploying EUV doesn’t just clear the way for future node shrinks. It slashes costs on the nodes where it’s deployed, hopefully giving customers who otherwise wouldn’t bother upgrading to a new node reasons to do so. That’s why GF, Intel, Samsung, and TSMC are all plunging ahead to deploy the technology even as Imec sounds the alarm on the difficulties ahead. It’s not an either/or situation. EUV has major problems still to be solved and EUV is a necessity for moving the industry forward.

The next few years are going to be real interesting.

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