TSMC Announces First EUV 7nm Risk Production, 5nm Tapeouts in Q2 2019

The foundry business was shaken earlier this year when GlobalFoundries announced it would leave the leading edge and no longer planned to offer a 7nm process. TSMC, on the other hand, is eager to tell its customers that new node ramps, including the introduction of uncertain technologies like EUV, are proceeding on schedule.

As EETAsia discusses, the firm has now taped out its first 7nm design to use EUV (Extreme Ultraviolet Lithography). EUV’s introduction has been nearly two decades in the making and the technology faces continued challenges as it ramps to lower nodes, but the way seems clear for its early insertion into manufacturing at this stage.

TSMC is also looking to offer new packaging options to help chip firms design faster products. As nodes shrink, wire resistance has become an increasingly dominant reason why clocks can’t be scaled up more effectively, and there are some packaging alternatives that offer theoretical improvements to these issues. It’s an example of how foundries are having to incorporate technology that touches on multiple aspects of the design and manufacturing process in order to continue delivering improvements rather than being able to count on lithography scaling to deliver the usual performance jumps year-on-year. The overall ramp of EUV is expected to be slow, as shown in the image below:

The announcement specifies that it taped out an EUV design that can use that technology on up to four layers, while the 5nm node will be capable of deploying EUV on up to 14 layers. One of the challenges to deploying EUV at 5nm is the current lack of a pellicle solution; this design presumably uses EUV for contacts and vias, which don’t require a pellicle (a pellicle is a protective, transparent shield that prevents debris from falling on the wafer). The problem with pellicles as they relate to EUV is that it’s very difficult to make a pellicle that’s completely transparent to EUV light (extreme ultraviolet light is absorbed by virtually everything, including ambient air, which is why EUV tools have to operate in near-vacuum conditions).

The 7nm TSMC is shipping now is based on conventional lithography rather than EUV. EUV isn’t really expected to introduce anything new as far as performance or power is concerned. Its chief benefit is in making chips cheaper to build for foundries and enabling lower node scaling in the future. The 5nm node is predicted to offer a 15 percent performance improvement or a 20 percent power reduction (but not both) with an overall 45 percent reduction in area. It’s not clear what will come after 5nm — manufacturers have sketched out paths to lower nodes, but with EUV still held up over pellicle solutions and the continued departure of foundries from the leading edge (We’re down to Samsung, Intel, and TSMC), it’s not clear how much of a runway still exists for companies to continue advancing the collection of technologies that we collectively refer to as “Moore’s law.”

If TSMC is able to enter risk production in Q2 2019, we could see chips in-market 12-15 months later, in 2020. That would put TSMC’s 5nm node with EUV up against Intel’s conventional lithography at 10nm, assuming Intel’s 10nm is indeed in-market by that point. AMD’s decision to move its products to TSMC means that the two firms are in direct competition again, though AMD has made no announcements about any 5nm migration and could skip the node if it turns out to be more of a mobile product, in much the same way that it skipped 10nm.

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