Report Claims Apple Will Use TSMC for 5nm in 2020
There’s a new report claiming Apple will use TSMC for 5nm production in 2020, despite the fact that first-generation EUV chips aren’t even coming off the line yet. If it proves true, it would mean TSMC is already locking up orders on the far side of one of the trickiest technical shifts the foundry world has ever made.
“TSMC is expected to secure the first 5nm chip orders from Apple for the 2020 iPhones,” according to DigiTimes. That’s significant because the level of EUV injection at the 5nm node is projected to be significantly higher than what we’ll see with TSMC’s second-generation 7nm node.
To recap: TSMC will use EUV at 7nm, but only for contacts and vias, the components that can be created without the use of a pellicle. According to an article by Mark LaPedus in SemiEngineering, there are three major issues to resolve: EUV uptime (currently between 70-80 percent, compared to 100 percent for conventional scanners), EUV mask yields (currently estimated at 72 percent in 2018), and the pellicle problem. A pellicle is a transparent shield that protects the photomask and prevents particles from falling on it. Even a single particle of dust can lead to a bad exposure and a failed part.
Uptime and mask yields have both been improving steadily for several years, but the challenges have been considerable. This quote from the article makes that point beautifully:
Today’s optical mask blanks consist of an opaque layer of chrome on a glass substrate.
In contrast, an EUV mask blank consists of 40 to 50 alternating layers of silicon and molybdenum on top of a substrate, resulting in a multi-layer stack that is 250nm to 350nm thick. On the stack, there is a ruthenium-based capping layer, followed by an absorber based on a tantalum material.
The article goes into further detail on the topic, but just the comparison between the two blank types illustrates how difficult just this single aspect of EUV has had to market. The pellicle issues are also complex. ASML, one of the major firms in the EUV tools business, has targeted a pellicle with an 88 percent transmission rate, rated to a 300W source, and capable of processing 10,000 wafers before replacement. Currently, ASML’s pellicle has an 83 percent transmission rate, withstands a 250W source, and must be replaced every 3,000 wafers.
TSMC has previously stated that it will use EUV much more extensively at 5nm, including on areas of the chip where a pellicle is required. ASML has said it intends to bring a pellicle to market that can meet its required specifications this year, though as we’ve detailed at length, EUV is possibly the poster child for “This year” claims that eventually are pushed back. At the same time, the foundry business is clearly committed to ramping EUV. We’ve seen double and quad-patterning deployed to extend the life of traditional lithography, but nobody is talking about a roadmap to 6-8 patterning steps.
If TSMC is already securing orders on 5nm, it implies the company’s overall solution for that node is shaping up well. Still, the roadmap to full EUV insertion has been made of rocks and at least 15 years of delays at this point. The fact that the industry is moving forward towards insertion does suggest that companies feel they will have solutions in place for these problems. The fact that it’s taken us decades to get here at all suggests the timelines could still shift a few more times.
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