SD Association Announces microSD Express With PCIe, NVMe Support

The SD Association has announced a new standard called microSD Express, with support for both PCIe the NVMe protocol to improve overall device performance. Devices that use the standard will be capable of up to 985MB/s transfer rates, courtesy of a single lane of PCIe 3.1 support. The new drives will remain backward-compatible with older cards — you’ll be able to read and use older microSD cards in microSD Express slots and microSD Express cards will still work in older readers.

PCIe 3.1 is PCIe 3.0 with various improvements to power management, performance, and functionality baked in. According to the SD Association:

PCIe 3.1 includes the low power sub-states (L1.1, L1.2) enabling low power implementations of SD Express for the mobile market. In addition, SD Express cards with significantly higher speed data transfer rates are expected to consume less energy than traditional microSD memory cards while keeping the same maximum consumed power. The cards provide system developers new options offered by PCIe and NVMe capabilities, such as Bus Mastering, Multi Queue (without locking mechanism) and Host Memory Buffer.

Multi-queue should improve concurrent I/O performance by reducing lock contention. Bus mastering allows a component — the microSD card in this case — to communicate with other components without needing CPU time.

In addition, Host Memory Buffer (HMB) lets the NVMe device use a small slice of system RAM to store the mapping tables that convert logical memory addresses to physical memory locations within the device itself. Without HMB, the device must either include its own DRAM or store this data on its own NAND flash. The first option is the fastest but costs both power and space, while the second is far slower.

HMB is a technique that improves performance compared with storing this data in flash, even if doesn’t quite match the performance of a DRAM pool onboard the device. There’s even a hint in the presentation that this flexibility could one day run both ways, allowing host devices to treat the microSD card’s NAND flash to operate an extension of main system memory, in much the same fashion that NAND flash can be used as a DRAM alternative today.

This is only a brief mention in the presentation and I’m not sure exactly which circumstances would make sense for this kind of buffering, so I wouldn’t read much into it. But it’s an interesting capability to see highlighted in the document.

If PCIe support for microSD cards can be slipstreamed into SoCs relatively easily and the power improvements are as good as the SD Association claims, I’d expect to see the technology adopted. Being able to save power is an important characteristic in modern devices, especially with power-hungry 5G modems on the horizons.

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