SiFive Announces First Out-of-Order RISC-V CPU, Boosts Efficiency, Per

SiFive Announces First Out-of-Order RISC-V CPU, Boosts Efficiency, Per

SiFive has deployed multiple CPU designs based on RISC-V already, but the U8 is the first to try and kick things up to competing with a design like ARM’s Cortex-A72. The goal is for the U8 to offer 1.5x performance per watt with 2x area efficiency and better design scalability overall, Anandtech reports.

SiFive Announces First Out-of-Order RISC-V CPU, Boosts Efficiency, Per

The U8 is a three-issue out of order CPU core with a 12-stage pipeline, which feeds three execution units. The instruction queue can only issue three instructions, but the decoder is four-wide. Typically, fetch is wider than decode, so we’re seeing something of a reversal here. Tremont recently used this strategy as well, so perhaps we’re seeing something of a trend in microprocessor design — or a design aspect that SiFive went for deliberately as part of building a scalable chip.

The current plans for the chip call for two models, a U84 and a U87. The U87 will be available later in 2020 while the U84 is being finalized. U84 IP is currently running on FPGA platforms and should be commercialized in the not-too-distant future as well.

SiFive Announces First Out-of-Order RISC-V CPU, Boosts Efficiency, Per

Overall performance is projected to be good against the A72 and should be competitive with ARM’s more recent chips as well. Whether it’ll be as good as estimated will have to wait for physical hardware to compare. SiFive will be building these chips on 7nm, so they’ll be on comparable process nodes to existing ARM-based chips. CPU clocks are said to be up to 2.6GHz, which is broadly comparable with where ARM chips are landing. I wouldn’t expect to see this kind of chip in smartphones — the amount of heavy lifting between SiFive and a phone is still enormous — but we could see them in more set-top boxes and embedded products.

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