IBM has claimed a world-first for its own labs, with “2nm” silicon now in production. All nanometer references in foundry press releases are essentially made-up numbers when used in this fashion. There is no single, defining feature in the chip that matches 2nm and is used for tracking progress in this fashion. Node names are defined by each foundry individually. This is how Intel can define a 10nm node with approximately the same transistor density as TSMC’s 7nm. This gap in numbers can create the illusion that one company is more advanced than the other purely based on a marketing metric.
The idea of using overall transistor density rather than node names has caught a bit in recent years. What IBM is calling 2nm has a transistor density of 333.33MTr/mm2 (million transistors per square millimeter). Intel’s 10nm has a quoted density of 100.76MTr/mm2, while TSMC’s 7nm has a density of 91.2MTr/mm2. This is where the common claim that Intel’s 10nm and TSMC’s 7nm are comparable comes from — Intel actually offers slightly higher transistor densities at the 10nm node than the Taiwanese foundry does on 7nm.
According to IBM, its 2nm node “is projected to achieve 45 percent higher performance, or 75 percent lower energy use, than today’s most advanced 7nm node chips.” This appears to be more or less in line with what we’d expect 2nm to deliver relative to 7nm after working out the math on what we know about TSMC’s 3nm so far. In most cases, foundry customers do not choose to emphasize only one trait or the other but decide to offer simultaneous improvements in multiple metrics.
“The IBM innovation reflected in this new 2nm chip is essential to the entire semiconductor and IT industry,” said Darío Gil, SVP and Director of IBM Research. “It is the product of IBM’s approach of taking on hard tech challenges and a demonstration of how breakthroughs can result from sustained investments and a collaborative R&D ecosystem approach.”
IBM continues to work in semiconductor research after selling its fabs to GlobalFoundries and turning to Samsung for its ongoing manufacturing needs. This work was performed at the SUNY Poly Nanotech Complex, where a number of companies maintain research facilities.
Designs of this sort are effectively pipecleaners intended to illustrate the viability of a node that isn’t ready for manufacturing yet. This new node uses nanosheets as a replacement for the 3D FinFET structures currently deployed in high-performance semiconductor nodes. Samsung has previously said it will shift to nanosheets at 3nm (TSMC intends to stick with FinFET for that node), while TSMC will shift at 2nm. Nanowires are expected to have advantages for low-power transistors, while nanosheets are better for high-power designs.
IBM’s research department is working well ahead of its actual silicon engineering. IBM will ship POWER10 CPUs later this year, built by Samsung on a 7nm process. 3nm silicon is expected in-market from TSMC by the end of 2022, with 2nm presumably following in 2023 or 2024, depending on whether or not development timelines slip.
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