Google reports that it is now using AI to build its future Tensor Processing Units. The company has published some work in this area before, about a year ago, but the announcement today indicates the technology has matured. Alexis Mirhoseini led the project.
The semiconductor industry has invested in various tools that automate parts of the design process for decades, now. Back when a CPU had 10,000 to 100,000 transistors, hand-drawn floor plans and circuit layouts were the only way to build a chip. Today, much of the design work is automated, though engineers may still be used in specific, critical paths.
Google is claiming it can adopt AI to help with floorplanning. The floorplan of a microprocessor — literally, its physical layout — has historically been a difficult task to automate. Even with the aid of modern software tools, laying out a new floorplan can take weeks. A great deal of work over many decades has gone into building software to better handle this complex problem, but humans are still integral to the process. Now, Google is claiming its new AI can do the job in a matter of hours.
Mirhoseini et al. estimate that the number of possible configurations (the state space) of macro blocks in the floorplanning problems solved in their study is about 102,500. By comparison, the state space of the black and white stones used in the board game Go is just 10360.
Part of what makes floorplanning difficult is that chip designers must leave room in their block positioning for all of the wiring and interconnects that must be built. There has to be room for standard cell placement, and components need to fit into the space left for them after a design has been optimized for performance, not just beforehand. Floorplanning is an interactive, iterative process.
Mirhoseini and her colleagues have worked to develop a floorplanning tool that could work for many projects, not just Google’s own efforts.
The image above illustrates how a floorplan invented by AI differs from the one built by humans. According to Nature, this is the Ariane RISC-V processor. The AI took just six hours to transform the layout into something no human would build. According to the researchers, however, the new layout outperforms the old one.
The advent of these tools could be a huge boon for semiconductor design. As Moore’s Law has slowed, metrics other than lithography have become increasingly important to performance and power consumption. Factors such as interconnect power are now a significant limiting factor on modern processors; AMD’s Milan CPU has higher IPC than the previous generation Rome microprocessors, but interconnect power is higher for Zen 3 than Zen 2. Good layout tools could minimize power consumption more effectively.
The most surprising thing about this new tool may be that its layouts don’t need to be adjusted iteratively during the manufacturing process. Google is willing to put its money where its mouth is and has commissioned its next-generation TPU to be built using these principles and strategies. If that card shows a dramatic leap in performance or overall power efficiency, it will be considered proof that AI is capable of handling this task in a matter of hours, and handling it better than humans do — at least, under certain circumstances. It may still take a few years to adapt this approach for high-end SoCs — the Ariane is not nearly as complex as your typical high-end CPU — but this proof of concept will drive additional research if the next-generation TPU pans out.
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