Neo Semiconductor Claims It Can Deliver QLC Density, SLC Performance

In NAND storage, density, durability, and performance form the three points of the typical “iron triangle” that companies attempt to optimize. It’s a classic case of a “You can have any two of these three features” scenario. We can build very durable NAND with incredible performance and low density (single-level cell, abbreviated SLC) or NAND with excellent density and low durability and performance (quad-level cell, abbreviated QLC). Companies are now exploring penta-level cell (PLC) NAND, but it’s still not clear if such designs are commercially viable.

According to Neo Semiconductor, it’s developed a method of building NAND that offers the performance of SLC and the density of QLC. Neo Semiconductor first broke cover last year with a report that it could achieve this and the company is back in the news this week after being granted two new patents on its technology.

Patent grants are not statements of commercial value and although Neo Semiconductor makes some really interesting claims about its technology, the firm is also trying to persuade large commercial manufacturers like Samsung, Kioxia, and Micron to license its IP. We were unable to find a neutral third-party evaluation of Neo Semiconductor’s claims regarding X-NAND and it does not appear that any manufacturer has near-term plans to put this technology into production. This does not mean that Neo’s claims are untrue, but until a manufacturer announces plans to bring this technology to market, we won’t know how effective it actually is.

Neo Semiconductor claims that by redesigning aspects of NAND flash, it can improve QLC random read/write performance by 3x and sequential read/write speeds by 15-30x. Here’s how the company describes its own innovation in its whitepaper:

Conventional NAND requires 16KB page buffer to connected to the 16KB bit lines of each plane to perform read/write operations. Therefore, the read/write size is limited by the number of the page buffers. X-NAND architecture uses one page buffer to read/write 16 or more bit lines in parallel. This reduces the number of page buffers of each plane from 16KB to 1KB.

The idea here seems to be straightforward. Neo Semiconductor believes it can wire NAND to exploit parallelism in a manner that allows for a much effective page buffer per plane. This efficiency improvement could allow manufacturers to deploy more planes, increasing NAND performance without increasing NAND die size. Neo Semiconductor claims a 16x reduction in bit line capacitance and a corresponding (but unspecified) decrease in bit line RC delay. The whitepaper goes on to detail Neo Semiconductor’s vision for a three-bank system that allows the SSD’s SLC cache buffer to continuously empty itself back to QLC without ever running out of storage capacity.

This is where the company’s “SLC endurance and longevity with QLC capacity” claims come from. If this technique works as advertised, SLC buffers would essentially never empty until the drive was full. If you’ve ever done a lot of data copying to a TLC or SLC cache, the end result is typically 100-200GB of acceptable SSD performance, followed by some really excellent HDD performance. The ability to maintain SLC performance on a QLC SSD over 50-75 percent of the SSD’s capacity would be a substantial upgrade to what we have at present.

We’re not NAND design experts, so I discussed Neo Semiconductor’s whitepaper with a contact of mine who has worked in the storage and data center industries and knows a great deal about the low-level structure and design of NAND. According to this individual, there are some low-level inconsistencies in the paper that may reflect simple mistakes or attempts to obfuscate information, but they make it difficult to fully analyze what’s being proposed. At the same time, much of what is discussed is a plausible path forward and there might be real improvements here — it’s just difficult to tell.

While Neo Semiconductors claims that “X-NAND architecture can be implemented in any existing NAND flash memory technology,” adopting the company’s proposed designs would still constitute a significant change to the underlying architecture of NAND flash. Reducing bit line capacitance by 16x and increasing the number of planes to 16, along with the different page buffer configuration, all represent changes to the existing status quo.

What Neo Semiconductors is promising it can deliver would represent a real improvement to existing NAND technology. The idea of programming QLC NAND to store data in SLC fashion is not new, but parallelizing data flows to allow SLC cache to empty itself during ongoing operations would be a neat trick. If Neo Semiconductors really has their finger on a good idea, we’ll probably see one of the major NAND players rolling it out at some point in the next few years. Thus far, the company has not announced any major partnerships or development/commercialization projects.

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