Kioxia recently presented at the China Flash Market Summit, where it shared data on what kind of performance to expect from its upcoming PCIe 5.0 drives. Just as PCIe 4.0 doubled bandwidth compared with PCIe 3.0, PCIe 5.0 doubles up compared with 4.0. An x1 PCIe 5.0 lane will deliver the same bandwidth as an x4 PCIe 3.0 lane.
According to Kioxia, it can put that bandwidth to good use. The company is claiming sequential transfer rates of up to 14,000MB/s read and 7,000MB/s write. Read latency has dropped from 90us to 70us and write latency from 20us to 10us.
That works out to a 15 percent reduction in read latency over previous generation drives, combined with a 50 percent reduction in write latency. Kioxia was targeting this presentation more towards the enterprise, where metrics like read and write latency are more important, but consumer hardware eventually benefits from these changes in the end, even when the gains are subtle.
A Quiet Revolution in Storage Performance
If you step back and look at the larger PC market, we’re witnessing nothing less than a revolution in storage capabilities play out in real time. Ten years ago, the SATA-III standard offered a maximum of 600MB/s worth of storage performance. Today, companies are showing drives that are capable of 23x more performance. Even if we allow for the fact that Kioxia is quoting idealized, best-case numbers, the degree of improvement has been nothing short of massive — and it’s accelerated in recent years, thanks to the rapid-fire release of PCIe 4.0 and 5.0.
One potential concern for PCIe 5.0 and beyond is that these interfaces tend to draw a lot of power. The fast release cadence of more recent standards after the long pause for PCIe 3.0 raises the question of whether we could reduce board power by reducing lane count. An x1 PCIe 5.0 link is equivalent to an x4 PCIe 3.0 link or an x16 PCIe 1.0 connection.
The PCIe 6.0 standard is already at 0.71 (1.0 being release) and the final standard is expected to be released by the end of the year.
The fact that the PCIe 6.0 standard will be finalized at the end of 2021 means we probably won’t see products until 2023-2024 at the earliest, but if we use that later date the rate of progression has been tremendous. An x4 PCIe 6.0 slot will offer the same bandwidth as an x16 PCIe 3.0 slot.
This is why I’m curious how Intel and AMD will respond to the situation. For the last two decades, tests have consistently shown that PCIe bandwidth rarely matters that much to GPU performance.
If GPUs can hit identical performance levels with fewer lanes thanks to the rapid increase in PCIe 6.0 bandwidth, it could also free motherboard manufacturers to use them for other things. There are some users who might prefer a board with four NVMe ports, all connected directly to the CPU’s PCIe lanes as opposed to running through the southbridge.
Microsoft and Sony’s decision to focus heavily on storage performance for the Xbox Series S|X and PlayStation 5 are a further indication of where the industry as a whole is headed, and an exciting preview of things to come. As the computer industry transitions away from spinning disks there are new opportunities to rethink, improve, and accelerate the storage stack — including via the time-honored method of throwing more performance at it, as Kioxia has demonstrated.
Intel will launch PCIe 5.0 support with its upcoming Alder Lake platform. Hardware is not expected to be widely available until 2022 at the earliest.