Intel Plans to License Hybrid Chips That Combine ARM, RISC-V, and x86

When Intel CEO Pat Gelsinger returned last year, he unveiled plans for a new IDM (Integrated Device Manufacturer) 2.0 strategy. Instead of only building its own CPUs, Intel wants to manufacture chips for companies across the planet. It’s made major recent investments in the RISC-V ecosystem and pledged to license x86 designs to customers.

In the future, Intel will license both hard and soft versions of various CPU cores to its customers. A “soft” core is a CPU core implemented in programmable logic, often in an FPGA. A “hard” core is a CPU core that’s implemented in physical silicon. The conventional chips sold by AMD and Intel are hard cores.

Intel is referring to the chiplet design we referenced last week as a “chiplet chassis” and envisions a chiplet design in which x86, ARM, and RISC-V all co-exist on the same physical silicon. According to Bob Brennan, Intel’s VP of customer solutions engineering at Intel Foundry Services (IFS), Intel believes there will be a long-term market for these type of products, with each IP devoted to a particular type of best-fit workload.

“In the chiplet chassis, we expect there will be demand for Arm and RISC-V, depending on which customer it is, and will support both,” Brennan told the Register. “We have not fully developed our strategy, but the concept is similar in that we want to enable the ecosystem of IP around our products.”

Intel’s Hybrid Future

Intel and x86 are practically synonymous with one another, even though Intel has built multiple non-x86 CPUs throughout its history. IFS’ declarations of support for RISC-V and ARM emphasize that the company is charting a new course for itself.

Intel envisions a world in which chip designers deploy differently optimized microarchitectures for different tasks. In this scenario, a vendor might use multiple RISC-V cores as dedicated I/O accelerators but with an x86 server CPU core and an ARM security processor. Another vendor might build a low-power x86 CPU with an even lower-power RISC-V AI accelerator. Esperanto, one of Intel’s recently-announced RISC-V partners, discussed such an accelerator at Hot Chips last year.

Over the last year, Intel has launched multiple hybrid x86 CPUs with low-power and high-power cores sharing the same silicon. The idea of marrying x86, ARM, and RISC-V silicon in the same package and connecting the cores via chiplets is a more advanced iteration of the same concept.

Intel’s vision is a significant departure from the status quo. Historically, companies have not built SoCs that mixed and matched microarchitectures in this way. The argument here is that mixing and matching CPU ISAs and connecting hardware via chiplets is conceptually similar to the way GPU computing has augmented and expanded workloads that were once the sole province of CPUs.

Long-term trends in the semiconductor industry may encourage this kind of consolidation. Chip density continues to scale, making it cheaper to build more advanced functions into the same area. Specialized accelerators that only light up occasionally draw less power than an array of constantly active generalist cores.

Enabling Assumptions

Intel’s argument rests on the idea that customers have use cases where multiple ISA’s make sense. This is an untested hypothesis. Intel has not yet announced any customers with plans to build a chip that supports x86, ARM, and/or RISC-V in the same package.

There’s a connection between Intel’s aggressive foundry expansion and its plans to support multi-ISA manufacturing. Intel institutionally believes that its control of CPU manufacturing is vital to its own long-term success and profitability. Supporting multiple ISAs gives Intel the best chance of winning business from the widest range of customers.

IFS wants to position itself as the foundry of choice for customers on the cutting edge, with packaging, lithography, and integration options not available elsewhere. In order to sell ISA integration as a specific feature, Intel needs to build a chiplet ecosystem that supports it.

Intel plans to introduce multi-ISA technology on two nodes. First, there’s Intel 16 (formerly known as Intel 22FFL). It’s a relaxed 14nm node originally intended for Intel customers during its first foundry push. Intel will also bring this capability to market when it offers what it now calls Intel 3. As far as Intel’s old nomenclature, Intel 3 is roughly where we’d expect a hypothetical Intel 7nm+ to be. Offering a mixture of mature and cutting-edge nodes allows IFS to market its services to a broader clientele with a wider range of use cases and products.

Intel’s long-term success may depend on whether its customers embrace the idea of multi-ISA devices. It’s certainly not the conventional way of doing things, but the idea may align with long-term semiconductor integration trends.

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