Intel’s Meteor Lake Tiles Will Be Made Mostly by TSMC

Intel’s 14th generation Meteor Lake CPU slash System on a Chip (SoC) has been in the news a lot lately. Even though its predecessor Raptor Lake has yet to launch, all eyes are on Intel’s future plans. That’s because Meteor Lake marks the company’s first node shrink in several years, and it’s also the company’s first tile-based design. There’s a lot riding on this one, in other words. It’s been previously reported the company was delaying it due to issues with its CPU tile or possible problems with TSMC’s tiles.

At the HotChips 34 conference this week, Intel cleared the air about the rumored delays (there are none), and the company provided more info on its tile-based design. As it turns out, three of the four tiles it’s using will be made by TSMC.

Backing up a tiny bit, Meteor Lake was always a four-tile design. However, it was originally thought Intel would be responsible for the I/O and CPU. TSMC would be crafting the GPU and SoC tiles. Meteor Lake’s ingenuity is that it allows for tiles built on different nodes to be used on the same chip via Intel’s Foveros stacking technology. This lets Intel use the “best node for the job,” so to speak. If a low-power tile is needed for one tile, but not the others, they can be combined. Originally, TSMC would use its N6 node for the SoC and its brand new N3 process for the GPU. Intel would be pitching in with I/O and CPU tiles made on Intel 4, formerly known as 7nm.

That’s now changed, as Intel will allegedly be using TSMC’s N5 process for the GPU instead. This was previously reported as a rumor, and Intel still hasn’t confirmed it. However, Tom’s Hardware notes that “industry sources” have confirmed the use of TSMC N5. This will likely cause Intel to reduce the number of execution units in the tGPU (tile GPU). It’s reportedly lowering the EU count from 192 on TSMC’s N3 process to just 128 EUs via TSMC N5. It will also reportedly be based on the company’s Battlemage architecture. Intel says its plans for the GPU node have not changed, however.

Another big ripple is the company is now reportedly outsourcing the I/O tile to TSMC’s N6 node as well. That means that TSMC is creating three of the four tiles needed for the chip. That leaves only the CPU tile to Intel. Prior rumors had Intel even outsourcing that tile over issues with its Intel 4 process. However, those rumors seemed ridiculous at the time and seem to be confirmed as false now. That tile was reportedly the reason behind an alleged delay of Meteor Lake. At the conference though, Intel stated Meteor Lake is still on track for 2023. It seems it just had to reshuffle the tile responsibilities a bit to hit its deadline.

Another bit of new information is the interposer that sits underneath the tiles. This is Intel’s Foveros technology, which allows communication between the various tiles. It’s being built on a 22nm low-power node and will be made by Intel. The interposer, or baseplate, has no logic in it, although Intel offers a 16nm version of it with logic to its Foundry customers. Intel originally debuted this technology with Lakefield.

Overall, Intel seems confident enough in Meteor Lake’s progress to present it at the conference. Hopefully, that means all those rumors about it being delayed were just that: rumors. A major piece of the puzzle seems to be shifting more responsibility to TSMC instead of making tiles in-house. But the CPU tile is still being made by Intel, and that’s what will really matter.

It’s still striking that Intel is placing the bulk of the responsibility for a watershed architecture in the hands of one of its biggest foundry rivals. Intel obviously wants to bring all that fab work in-house, which it will likely due on a future node.

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