Intel Denies Media Reports Claiming It Cancelled Its 10nm Process

It’s no secret that Intel’s 10nm process has been bedeviled by delays and problems — the node is years late already, and it may not debut at volume until Q4 2019. But new media reports suggest that Intel has cancelled the node completely, while Intel itself denies that charge.

The claim is from SemiAccurate, which writes that “Now we are hearing from trusted moles that the process is indeed dead and that is a good thing for Intel, if they had continued along their current path the disaster would have been untenable. Our moles are saying the deed has finally been done.” SemiAccurate has indeed been predicting that Intel would cancel or substantially revise its 10nm node with less aggressive targets for ramping it.

Intel contests this claim:

Media reports published today that Intel is ending work on the 10nm process are untrue. We are making good progress on 10nm. Yields are improving consistent with the timeline we shared during our last earnings report.

— Intel News (@intelnews) October 22, 2018

Unfortunately, it’s not possible to see the actual evidence SemiAccurate provides (archival link, the site is down) for its argument because that information is subscriber-only. It’s difficult, therefore, to test the evaluated claims. But the better question to ask, given the paucity of information, is this: Regardless of whether Intel canceled its previous 10nm process, would Intel walk away from being a leading-edge foundry? And the answer there is an obvious “No.”

There is a multitude of reasons why Intel won’t accept this outcome, starting with the fact that it’s tantamount to ceding future progression to outside companies. And in this context, ” canceling” 10nm could mean something more akin to “drawing up a new plan for future node progression” as opposed to “walking away from the leading edge forever,” even assuming SemiAccurate’s rumors are correct. There’s too much at stake as far as Intel’s perceived manufacturing prowess. Leading edge development is simply too important to the company to quit.

If the SA rumor is right, we’ll likely hear about it before long. Intel, having previously repeatedly committed to a 10nm ramp in Q4 2019 will have to publicly notify its partners and investors about any delay, just as it notified them about the previous ones. The more likely course of action would be for Intel to still push forward with a “10nm” node with different characteristics — possibly one more relaxed than the company’s incredibly ambitious hyperscaling project, which seemed a tough approach when it was proposed back in 2017 and hasn’t managed to launch since. Intel’s original 10nm slideshows and our commentary from its launch day are both embedded below:

Intel is claiming significant improvements on fin pitch, minimum metal pitch, cell height, and gate pitch, with two new technologies tossed in for good measure.

This slide shows the space savings from using a single dense dummy gate rather than two gates separated by a larger space. Intel claims this improvement can provide up to 20% effective area scaling benefit.

Moving the contact to directly under the transistor saves Intel another 10% in effective area scaling.

Here's how Intel gets to the 2.7x "hyperscaling" it refers to elsewhere. It's not just about die shrinks, but about the secondary technologies baked into them.

Since most people don’t know the difference between different nodes or node-types, Intel can slide an updated process node into place and call it 10nm. Node names are basically marketing titles these days, so the substitution would go unnoticed among the general public — and if the new node’s performance is good enough, it could go largely unremarked among the technical press as well, beyond reports of the differences as a matter of factual accuracy.

This slide summarizes why Intel wants a different metric for process nodes. Even compared to the "other" 14nm, its transistor density is still 1.23x higher. Note: We do not know which specific process nodes at Samsung or TSMC were compared against Intel's products.

Underlying Intel's argument for the continuation of Moore's Law is that its 10nm will be a larger improvement on its 14nm transistor density than any previous generation.

The same graph as the previous slide, but with raw numbers on transistor density instead of scaling points.

In terms of transistor gate pitch, 20nm and first-generation 14nm/16nm were roughly comparable to Intel's 22nm node. A later 14/16nm product has improved on that metric but still lags Intel's three-year-old node.

The pure-play foundries compare better against Intel in metal pitch scaling, but they still don't match Intel's 14nm, much lets its 10nm target. Again, they're projected to deploy 10nm at something closer to Intel's 14nm.

The pure-play foundry business is expected to exceed Intel's 14nm transistor density once they build 10nm products in volume, but Intel believes its 10nm density will be significantly better.

There are two interesting things on this slide. First, it confirms that Intel *will* deploy a 14nm++ node, as previously rumored, and that its first generation 10nm won't offer equal performance. Today's Kaby Lake customers will have to wait for 10nm++, expected in ~2020, to see transistor-level performance improvements above and beyond what Kaby Lake offers.

Our final thought is this. While it’s true that Intel’s 10nm slips have already been unprecedented, regardless of whether this rumor is true, these problems do generally fit the theory we’ve talked about over the years: Specifically, node slips and problematic improvement cycles were going to become more normal than they used to be, as the difficulty of further improvement only grew. Intel isn’t the company we expected to slam into these problems first, but that doesn’t mean they aren’t real.

That doesn’t mean Intel hasn’t made mistakes throughout this process. But it does make those mistakes intrinsically more likely to occur.

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