Intel Details Its Upcoming Sunny Cove CPU Architecture

For most of 2018, it’s felt as though all the energy in the CPU market was coming from AMD‘s side of the equation. While multiple companies have been affected by issues with Spectre and Meltdown, Intel took the brunt of those impacts. It’s also weathered a major 10nm delay (again) and dismissed its CEO — ostensibly for a consensual relationship with an employee. But while these events have knocked Intel off its stride, they haven’t derailed the company’s long-term efforts to bring new products to market.

Today, Intel took the wraps off Sunny Cove, its first new CPU architecture since Skylake. Intel hasn’t completely detailed the underlying architecture, and certain details, like the back-end, are still unclear. But Intel has decided to open the curtain much more thoroughly than it typically does at this stage of development. Each slide is covered in the slideshow below. Each slide can be clicked to open it in a larger separate window.

Compared with Skylake, Sunny Cove will be capable of issuing two loads and two stores per cycle, rather than the 2L,1S of Skylake. There are four AGUs now, up from three, 10 ports (up from 8), a second shuffle unit, and a second LEA (Load Effective Address) unit.

The L1 data cache on Sunny Cove is 50 percent larger than Skylake and previous Intel chips, at 48KB compared with 32KB. Larger L2 caches, a larger uop cache, and expanded L2 TLB cache are other features planned for the architecture.

L1 store bandwidth has been doubled, with a wider array of capabilities for the execution ports. The design also now features 4 LEA (Load Effective Address) blocks.

Finally, Intel claims to have improved branch prediction efficiency, with additional latency improvements across the chip and a new integer divider unit.

In addition to these improvements, Sunny Cove offers specialized support for new instructions, 57 bits of linear address support, and 52-bits of physical address support. There are now five levels of paging, up from four, and new security modes, including User Mode Instruction Prevention, a new mode that

If enabled, it prevents the execution of certain instructions if the Current Privilege Level (CPL) is greater than 0. If these instructions were executed while in CPL > 0, user space applications could have access to system-wide settings such as the global and localdescriptor tables, the task register and the interrupt descriptor table.

Intel’s overall roadmap for its next-generation Core and Atom products can be seen here:

The chart suggests Intel is adopting a yearly cadence for performance improvements. The relative positions of each chip are inaccurate; we asked and were told that Sunny Cove is the 10nm CPU Intel has promised to have on store shelves for holidays, 2019. Willow Cove and Golden Cove will arrive later, presumably in 2020 and 2021.

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