How AMD’s Zen 2 Architecture Boosts Performance-Per-Watt

With the launch date of AMD’s upcoming Zen 2 architecture fast approaching, the company has pulled back the curtain and given us a view into the capabilities and improvements of its new uarch. These new chips include a number of improvements and benefits to drive both higher instructions per cycle (IPC) and better overall power consumption.

One point AMD Corporate Fellow Mike Clark made during his presentation on Zen 2 is that its 7nm transition was actually more successful than it initially predicted.

Some of you may recall rumors that AMD would field Ryzen 3000 CPUs with far higher CPU clocks than previous parts. According to AMD engineers, the company did not necessarily expect Zen 2 to hit higher frequencies at all. This is the intrinsic problem of modern CPU node shrinks. Smaller process needs mean lower voltages, and lower voltages can have negative impacts on absolute operating frequency. In this case, however, TSMC’s 7nm node and AMD’s own engineering were able to create parts that could hit modestly higher frequencies than 12/14nm chips.

The fact that AMD did not expect to necessarily see clock frequency improvements on 7nm is something to keep in mind when evaluating the accuracy of rumors about massive clock jumps in the future.

One important change coming with Zen 2 has nothing to do with the actual CPU itself. AMD notified us at the event that there are new scheduler changes incorporated into the Windows 10 Scheduler as of Windows 10 1903 (May 2019 Update). There are two new capabilities: Topology Awareness and faster clock ramping. Faster clock ramping reduces the amount of time for the CPU to switch clock states, improving performance and theoretically improving idle power consumption by allowing the CPU to shift to lower clock states more quickly. Topology awareness should help keep data local to appropriate CCXs and fill one CCX before loading another.

These gains — +15 percent 1080p performance in Rocket League and a 6 percent improvement in PCMark 10 application launch — are solely the result of the Windows 10 scheduler update, and are separate from any additional gains as a result of improvements to the Zen 2 architecture. Taking advantage of these improvements requires both an updated chipset driver and the Windows 10 1903 update.

This slide represents AMD’s big-picture microarchitectural overview. The chip integrates a new TAGE branch predictor in addition to the perceptron BP it has used in the past. The micro-op cache has been increased to 4K instructions, with double the total L3 onboard. (AMD is now referring to its combined L2 and L3 as “AMD GameCache.) There is now a new address generation unit (AGU) attached to the integer side of the core, with full support for 256-bit floating point via AVX2.

Architectural Improvements

The slideshow below contains our deep dive into the specific architectural enhancements of the third-generation Ryzen CPU. Each slide can be clicked to open it in a new window.

The L1i cache has been shrunk to 32KB, from 64KB, but its set associativity has increased. AMD found that the larger L1i wasn't needed with the new design, and rebalanced its silicon accordingly. Work has been pushed into the faster L0 cache when possible, leaving less need for the larger L1. There are also some security improvements to AMD's SMT implementation when running VMs.

BTB (Branch Target Buffer) sizes have been increased. The new TAGE branch predictor (TAgged GEometry). A TAGE predictor is a hybrid design that tracks branch histories more accurately. Improvements to branch prediction are critical to boosting CPU performance because failing to predict a branch correctly causes pipeline stalls. AMD's perceptron BP is still its first-level branch predictor, TAGE is the second-level BP.

AMD's decode stage benefits from improvements to the opcache and a 2x larger buffer for fused instructions. The specific types of instructions that can be fused were also tweaked, and overall instruction throughput improved.

There are major improvements to the FPU unit. The Zen 2 architecture now supports 256-bit AVX2, with double the floating-point load/store bandwidth. The latency of specific instructions has been improved, including cutting mul latency to 3 cycles. Unlike Intel, AMD does not specifically set a lower clock speed for the CPU when running AVX2. This doesn't automatically mean the CPU clock won't drop in AVX2 code, but Intel defines a static lower multiplier to ensure its chips remain within tolerances. According to Clark, AMD has not been forced to take this step thanks to the improvements of 7nm. Physics simulation, inline memory copies, and audio effects processing should all benefit from the various instruction tweaks and wider AVX processing options.

The integer scheduler is wider now, with a higher number of entries. The core has been expanded to keep a higher number of instructions in flight and to hold more data in various buffers to accommodate the additional AGU unit and to improve overall throughput. SMT performance has also improved in some scenarios due to better workload balancing between the ALU and AGU units.

The load/store unit has been improved as well, with a larger L2 DTLB, a larger entry store queue, and double the load/store bandwidth thanks to increasing bus width to 32B/cycle, up from 16B/cycle. Buffers are no longer closed before they are completely full, improving overall performance and boosting efficiency. The CPU's internal prefetching has been tuned to be less aggressive in certain scenarios to increase power savings.

There's not much different about the Zen 2 cache hierarchy other than the change to the L1i cache. L1 load/store bandwidth has increased by 2x, with better prefetch throttling. The L3 cache is still a victim cache for L2 data. There are no CCX-to-CCX connections within the Zen 2 architecture — L3 data requested by Chiplet 1 from Chiplet 0 still moves across the I/O die.

According to AMD, these improvements leave them far ahead of Intel, both in terms of performance-per-watt and absolute power consumption at the wall.

Cinebench is not the be-all-end-all of power consumption measurement, but it’s not a bad test, either. The 3700X — which, in fairness, probably sits the closest to the overall sweet spot for the architecture — is supposedly 56 percent more efficient than the Core i7-9700K, while drawing just 86 percent as much power in absolute terms.

The gains against the 2700X in terms of overall power efficiency are even larger. AMD claims the 3700X is 1.75x more efficient in perf/watt than the 2700X, while drawing 70 percent the power.

Conclusions

While we obviously can’t judge a launch until we have hardware to test, AMD is laying out an aggressive, exciting product family. TDPs have fallen dramatically. IPC has reportedly increased by 1.15x. Clock speeds have been bumped. The scheduler improvements and doubled-up floating point capability should provide their own robust improvements over and above this 1.15x figure. The Infinity Fabric bus width has been doubled to allow PCIe Gen 4 bandwidth to be fully utilized, and there’s a new memory divider at DDR4-3733 to allow for lower IF clocks without compromising DRAM scaling.

If you’re a fan of AMD’s APUs, 7nm has exciting long-term implications for them as well. While we don’t know when we’ll see these parts, the company has clearly aggressively targeted lower power consumption across the board. This will clearly pay off when it comes time to refresh the APU family on 7nm. One of our theories about the 7nm launch was that AMD would emphasize power-efficiency on at least some parts, and we’re absolutely seeing that, with a higher-performing 8-core CPU in a 65W TDP and a 16-core CPU in a 105W TDP.

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