The Ballad of AM4: How AMD Stretched a CPU Socket From 28nm to 7nm

Up until now, our E3 coverage has focused on the two major announcements AMD made around its upcoming CPU and GPU products. But the company also gave a few other interesting presentations, including one on the evolution of Socket AM4.

As Moore’s Law has slowed, manufacturers have turned to alternate methods of achieving the improvements they want to see from one generation to the next. Rather than relying on straight node shrinks to improve performance, they’ve turned to packaging as a way to eke out new gains. AMD’s Fury X GPU family, which debuted the use of HBM, is an example of how a packaging change can substantially reduce power consumption (memory subsystem power consumption in this case) while still providing significant gains. The shift to chiplets is one way companies are working through this problem — but chiplets still have to be connected together in a common socket standard.

AMD laid the groundwork for its modular chiplet approach back with first-generation Ryzen. While it didn’t have separate I/O die, the idea of building CPUs in their own discrete packages and connecting them via a common fabric was still a step towards the increased modularity of chiplets today.

One major challenge for AMD is maintaining pinout compatibility while shifting from a monolithic four-core die built on 28nm to a mixed-core plan with 14nm and 7nm silicon deployed on the same package. Keep in mind, there’s no way to change what pins carry which data. Enhancements and improvements to the socket can be made, but changing the socket design breaks backward compatibility.

AMD lowered its bump pitch from 150um to 130um for 7nm Ryzen, despite the challenges of doing so. There are only two vendors building these kinds of solutions at the moment. In order to make the shift effectively, AMD had to transition away from traditional lead-free solder bumps and adopt what are known as copper pillars, with a lead-free solder cap. This allows for markedly smaller bump pitches.

The 12nm I/O die would have used solder bumps by default, but 7nm chips use copper pillars for superior density. The I/O die had to be fitted with this solution as well in order to allow for a common interface. New materials and interfaces were also required for PCI Express 4.0 routing — AMD opted to use low-loss materials for the first time and categorized its own work in this area as “Taking some bets that paid off.”

The routing diagram for the underlying chip. You can see the two chiplets at the top of the die and the wire traces that connect them to the I/O die. The four rectangular blocks in each CCX likely correspond to the L3 cache.

These improvements are the first phase for chiplets and chiplet designs. The adoption of chiplets is still a very new phenomenon in the semiconductor industry. One reason we haven’t seen them used more widely yet, for example, is that there’s no common interface or standard for chiplet designs to use. This is where AMD and Intel have an advantage — both companies have experience in building fabrics to connect components and broad IP portfolios to provide the necessary function blocks. We’ll start seeing more companies experiment with these methods as time goes by and new standards emerge. Long-term, chiplets could theoretically be used to attach different IP blocks, each built with different materials or on different process nodes.

In this case, AMD’s chiplets are built on 7nm, the chipset is built on 14nm, and the section of the I/O die that actually handle I/O use 12nm — which is actually an optimized 14nm with tweaked design rules and libraries. (AMD has typically short-handed this by saying that the chiplets are 7nm and I/O is 14nm, but the company gave us a little bit of additional depth at its E3 deep dives).

AMD said nothing about the projected lifespan of AM4 or whether it would be moving to AM5 after 2020. The company reiterated that it intends to support the AM4 socket “through 2020” but said nothing about its plans thereafter. There’s talk of the first DDR5 modules being available possibly by the end of 2019 or early 2020, which means 2021 could easily be when we see the first mainstream DDR5 chipset — and AMD might well choose to introduce Socket AM5 to capitalize on the need for different routing and circuitry layouts to support new DRAM. This is conjecture, however, and the company has made no announcements.

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